The invention relates to a transistor, in particular to a trench transistor.
Power transistors have to process high current levels, which frequently leads to severe heating of the transistor. In order to prevent overheating of the transistor, temperature sensors are frequently integrated in transistors such as these. The temperature sensors may, for example, be integrated in a cell array in the transistor, or else may be formed in the immediate vicinity of the cell array, with the temperature sensor being electrically isolated from the cell array by an isolation structure. The isolation structure in general comprises an edge termination for the cell array as well as an edge termination for the temperature sensor. Since both edge terminations are arranged immediately adjacent to one another, the distance between the temperature sensor and the transistor cells in the cell array is relatively large. The resultant temperature gradient between the temperature sensor and the transistor cells leads to corruption of the temperature measurement. Another disadvantage is that the temperature sensor records the temperature in the cell array with a considerable time delay.
The problems mentioned above will be explained in more detail in the following text with reference to FIG. 7.
FIG. 7 illustrates a detail of a trench transistor 1 (DMOS transistor) in which an edge area 2 of a cell array as well as a temperature sensor 3 can be seen. The cell array has two or more active transistor cells 4, with an inactive edge cell 5 as well as an edge termination 6 being adjacent to the active transistor cells 4. The active transistor cells 4 have an n+-doped source region 7, a p+-doped body region 8, as well as an n-doped drift region 9. Each active transistor cell 4 is also bounded by trenches 10, with at least one electrode 11 being provided in each of the trenches and being electrically isolated by an isolation layer 12 from the semiconductor region which is adjacent to the trench 10. The electrode 11 is used as a gate, in order to induce a channel from the source region 7 into the drift region 9 through the body region 8. Isolation layers 13 are provided above the trenches 10. A source metallization layer 14 terminates the cell array at the top. There is no source region in the inactive edge cell 5. The edge termination 6 essentially comprises a trench 15 in which an electrode 16 is embedded, which projects upwards out of the trench 15. Furthermore, an n+-doped region 17 is provided, in order to suppress parasitic currents between the edge area 2 and the temperature sensor 3.
The temperature sensor 3 has a p-doped base region 18, which is in the form of a well region, as well as a base connection 19 and an emitter connection 20. A p+-doped region 21 is provided between the base region 18 and the base connection 19, and an n+-doped region 22 is provided between the emitter connection 20 and the base region 18. The field electrode, which is identified with the reference symbol 23, is optional and is part of the edge termination of the temperature sensor 3. The layers which are identified by reference symbols 24 and 25 represent isolation layers. FIG. 7 illustrates the equivalent circuit of the temperature sensor 3 (a transistor whose switched-off current is a measure of the temperature at the temperature sensor 3).
The lateral extent of the edge area 2, in particular the extents of the inactive edge cell 5 and of the edge termination 6, has an effect that is not negligible on the temperature measured by the temperature sensor 3. The active cells of the trench transistor 1 (that is to say the “heat sources”) are separated by about 40 to 100 μm from the temperature-sensitive area of the temperature sensor 3; the distance D1, which is illustrated in FIG. 7, is about six times the pitch between the active cells 4 of the cell array.
A trench transistor whose cell array temperature can be measured with as little corruption as possible would be a useful improvement.
If two or more mutually independent semiconductor functional elements, for example NMOS and/or PMOS transistors, are intended to be arranged alongside one another, then it is necessary to isolate the semiconductor functional elements from one another electrically (self-isolation) in order to avoid disturbing influences between the semiconductor functional elements. Known isolation structures for self-isolation of an NMOS transistor and of a PMOS transistor will be explained in more detail in the following text with reference to FIG. 14.
The upper part of FIG. 14 illustrates a (schematically simplified) edge termination of an NMOS transistor. A retrograde-doped p well 31 as well as a homogenously doped p well 32 are provided in a substrate 30. A first and a second isolation layer 33, 34 are arranged on the substrate 30, between which a p+-doped region 35 is formed. The p+-doped region 35 is electrically connected to a field plate 36, which is arranged on the second isolation layer 34. Furthermore, a gate 37 is provided above a part of the retrograde-doped p well 31.
The lower part of FIG. 14 illustrates a (schematically simplified) edge area of a PMOS transistor. A retrograde-doped p well 41, a homogenously doped p well 42, a homogenously doped n well 43 and an isolation well 44 are formed in a substrate 40. A first and a second isolation layer 45, 46 are formed on the substrate 40, between which a p+-doped region 47 is provided. The p+-doped region 47 is electrically connected to a field plate 48 which is provided on the second isolation layer 46. A gate 49 is provided above a part of the n well 43.
The edge structures that are illustrated in FIG. 14 require a large amount of space in order to provide a desired withstand voltage, and to prevent an electrical field from punching through (the punch effect) into undesirable regions, and the formation of parasitic channels, in particular of PMOS channels between two adjacent wells.
A transistor component that has two or more functional elements that are arranged alongside one another and can still be adequately isolated from one another even with an increased integration density would be a useful improvement.
For these and other reasons there is a need for the present invention.